It took humanity about 100 years to miniaturize the vast power grid into vacuum tubes and integrated circuits, ushering in the digital age; but in the era of large-scale models, electrical problems have pulled digital systems back to the physical world. The greater the computing power and the more complex the system, the more important simulation becomes.
On May 20th, Nvidia announced its first-quarter results for fiscal year 2027, ending April 26, 2026, with quarterly revenue reaching $81.6 billion, an 85% year-over-year increase; data center revenue reached $75.2 billion, a 92% year-over-year increase. The same trend was observed in the storage sector. SK Hynix stated in its second-quarter 2025 report that it plans to increase spending on advanced chip manufacturing, primarily on HBM-related equipment, and that full-year HBM sales are expected to double compared to the previous year.
The explosive growth of AI has made Nvidia one of the most dazzling companies in the global semiconductor industry, and has also made high-bandwidth memory one of the most scarce resources in AI servers. The first wave of AI dividends went to GPUs and HBMs, and at the same time, we are seeing the second wave of dividends spreading to analog chips.
Analog Devices (ADI) recently acquired Empower Semiconductor for $1.5 billion in an all-cash deal, sending a clear signal: competition in the AI industry chain is shifting from explicit computing power components like GPUs and HBMs to underlying support components such as power supplies, power management, and signal integrity. Analog chips are no longer just background devices, but are becoming a key variable in the continued expansion of AI infrastructure.
The ultimate goal of AI is not just computing power, but also energy; and the control of energy and signals ultimately cannot be separated from simulation.
Computing power surges, power supply dwindles
As AI systems move from standalone machines to rack-mounted systems, and from clusters of tens of thousands of cards to hundreds of thousands or even millions of cards, the "computing power bottleneck" of digital chips encounters the relentless limitations of physical laws.
The power shortage in data centers is turning from a prediction into an imminent crisis.
The International Energy Agency (IEA), in its "Energy and AI" report, indicates that global data center electricity consumption was approximately 415 TWh in 2024, accounting for about 1.5% of global electricity consumption. By 2030, data center electricity consumption is projected to more than double, reaching approximately 945 TWh. The IEA also specifically points out that AI is one of the most important drivers of this growth; the electricity consumption of accelerated servers is expected to grow at an average annual rate of 30%, contributing nearly half of the net increase in global data center electricity consumption.
The Stargate project, spearheaded by OpenAI, Oracle, and SoftBank, can be seen as a landmark example of this trend. OpenAI disclosed in September 2025 that after adding five new US AI data center sites, Stargate, along with projects like Abilene and CoreWeave, will have a planned capacity of nearly 7GW, with investments exceeding $400 billion over the next three years, moving towards its previously announced $500 billion and 10GW commitment.
The bottleneck of AI systems is no longer just "whether we can build a faster core", but has sunk to issues such as power distribution, power consumption conversion, signal integrity and heat dissipation limits.
Without a good power source, computing power is just a castle in the air.
800V DC architecture drives a revolution in vertical power supply.
This is why Nvidia has started to personally promote the 800V DC architecture.
In 2025, NVIDIA proposed an 800V DC power architecture for its next-generation AI Factory. Its official technical blog points out that traditional 54V rack power supplies, originally designed for kW-level racks, are not suitable for the upcoming MW-level AI racks; NVIDIA plans to begin promoting 800V DC data center power infrastructure from 2027 to support IT racks of 1MW and above.
Why move from 48V/54V to 800V? It's a purely physics and engineering mathematics problem. According to Joule's law: P=IxV, Ploss = I²xR. When rack power (P) soars from tens of kW to over 1MW, if the low-voltage 54V supply continues, the current (I) will reach an astonishing tens of thousands of amperes.
The enormous current means extremely high transmission losses (proportional to the square of the current). Traditional power supply methods are mostly horizontal: the power module is placed somewhere on the motherboard or accelerator card, and the current flows horizontally to the processor core through the PCB copper layer, vias, and solder balls. However, when the current reaches hundreds of amperes or even higher, this seemingly short path will generate significant resistance losses, voltage drops, and heat.
As GPUs (such as Blackwell and even next-generation architectures) draw currents exceeding 1000A, power supplies face two major vulnerabilities: the first is transient response latency: when the GPU is momentarily at full load, if the power supply is far away, the voltage will drop instantly; the second is parasitic resistance loss: lateral power supply (leading from the edge of the PCB to the center of the chip) can cause severe voltage drops.
Nvidia points out that in a 1MW single-rack scenario, using a 54V architecture would require copper busbars weighing as much as 200kg just for transmitting current, not only taking up valuable server space but also making cabling impossible. Moving to 800V DC significantly reduces current, resolving copper loss and space constraints. Nvidia's envisioned Kyber rack architecture uses centralized high-voltage DC transmission, with a high-ratio converter near the compute nodes to reduce the voltage to below 12V in one step. Nvidia claims that this single-stage conversion solution reduces the footprint by a full 26% compared to traditional multi-stage conversions.
This is not a minor tweak, but a change at the power architecture level. This drives the demand for vertical power supply and near-core power supply .
Vertical power supply is arguably the most advanced power supply technology in the HPC field today. It integrates the voltage regulator (IVR) and silicon capacitors directly into the chip package, even stacking them directly beneath the GPU, and injects current vertically into the wafer core via micro-bumps, much like "injections." Power supply technology and chip packaging technology are completely integrated here.
The value of vertical power supply lies in compressing this "last path." It attempts to move power conversion, decoupling capacitors, and power integrity management closer to the load, and even deliver current more directly to the vicinity of the computing core through low-impedance paths under the package or chip. In this way, the system can reduce the voltage drop and heat loss caused by lateral power supply, while improving transient response capability when the load changes rapidly.
Now, Nvidia is teaming up with giants like ADI, Infineon, MPS, Navitas, Onsemi, Renesas, ROHM, ST, and TI to discuss "how to implement this power supply architecture and how much space to allocate for the power supply within the package" from the early stages of chip design. The power supply is no longer just a peripheral circuit; it is itself the underlying architecture of the computing infrastructure.
ADI acquires Empower:
Securing the "near-core power supply" ticket
Amidst Nvidia's promotion of the 800V ecosystem, ADI has recently made a significant investment.
On May 19, ADI announced its acquisition of Empower Semiconductor for $1.5 billion in an all-cash deal. ADI has publicly stated its intention to become a "Grid-to-Core" power partner for hyperscaler and AI chip manufacturers.
The term Grid-to-Core can be understood as a complete power supply chain that runs from the data center's power input downwards, covering high-voltage power distribution, rack power supplies, server power supplies, board-level power supplies, and finally reaching the vicinity of the GPU/ASIC core.
Empower is the key to ADI achieving this goal. Empower's core selling point that attracted ADI is its near-core power supply and vertical power supply.
Empower's core technologies are IVR (Integrated Voltage Regulator) and silicon capacitors. It can integrate power management modules directly at the silicon wafer level, or even in a 3D package, placing them directly below the GPU chip for "vertical power supply." This helps customers reduce the power supply footprint by up to four times and is expected to reduce data center computing power consumption by 10% to 15%.
To understand the importance of this route, Vicor is a good reference.
In the field of vertical power supply, Vicor is one of the earliest manufacturers to systematize the relevant architecture. Its underlying concept is Factorized Power Architecture (FPA), which breaks down the traditional power conversion process into different functional modules, and then uses high-density modules to achieve efficient conversion and current multiplication.
Regarding power supply methods closer to the processor, Vicor primarily proposed two types of paths:
LPD, Lateral Power Delivery: The power module is placed around the processor to supply power to the processor from the side;
VPD, Vertical Power Delivery: This involves placing the power module further below the processor or near the package to shorten the current path vertically.
According to Vicor's official documentation, its architecture can combine LPD and VPD to reduce the power supply impedance of the "last inch"; related solutions can reduce motherboard resistance by up to 50 times and reduce the number of processor power supply pins by more than 10 times.
Empower and Vicor do not follow the same specific path, but they are heading in the same direction: power supplies are moving from the board level to near the package, from lateral power supply to near-load or vertical power supply, and from competition for single devices to competition for system-level power supply architectures.
Analog and power manufacturers are fiercely competing for market share.
Traditional general-purpose power supply (PMIC) chips compete on cost, scale, and shipment volume; while HPC power supplies compete on extreme material science, topology innovation, and topology control algorithms (digital power control). This explains the frenzied mergers and acquisitions and competition for high-performance power supply companies in the semiconductor industry over the past year. Whoever can secure a place in the ceiling-level HPC power supply field will essentially have obtained a ticket to the most lucrative and highest-barrier market in the AI era.
Faced with the disruptive opportunities brought by 800V high-voltage DC, 48V architecture, high-density modules, and near-core power supply, global analog and power semiconductor manufacturers are showcasing their unique strengths and engaging in a cluster-like competition for next-generation AI power architecture. Broadly speaking, this competition is forming several different technological routes.
TI & ST: Reduce the number of conversion stages
Texas Instruments (TI): Adopting a "high-density, low-stage" approach. In March 2026, TI and NVIDIA showcased a complete 800V solution, requiring only two conversion stages from 800V to the GPU core power supply: an 800V to 6V isolated bus converter, and a 6V to below 1V multiphase buck converter. The 800V to 6V DC/DC bus converter utilizes an integrated GaN power stage, achieving a peak efficiency of 97.6% and a power density exceeding 2000W/in³.
ST is also betting on two-stage conversion. In March 2026, ST launched an architecture that jumps from 800V to 6V/12V. ST stated that the 800V to 6V path allows the 6V bus to be closer to the GPU, reducing the number of conversion stages, copper usage, and resistor losses, while improving transient performance.
TI & ST and ADI+Empower's near-core power supply logic is not exactly the same, but the direction is the same: the closer to the computing core, the higher the value of the power supply.
MPS: High-density modular power supply
MPS is an indispensable player in the AI/HPC power supply arena. It doesn't simply provide a single DC/DC chip; rather, it has long focused on the power supply needs of data centers and AI GPUs, entering the market with high-density power modules, 48V architecture, intelligent power integration, and digital control.
This is also the real challenge in the AI power supply field: it's not about "whether you can make power chips," but rather whether you can deliver extremely large currents to the vicinity of GPUs/ASICs within a limited board space with sufficiently high efficiency, fast transient response, and low heat dissipation. This tests your comprehensive capabilities in chip design, packaging, layout, thermal design, and customer platform verification.
Infineon & Renesas: Leveraging their strengths in third-generation semiconductors and control
Infineon: Infineon focuses on its strengths in "high voltage, high current, and high reliability." They concentrate on using SiC/GaN devices, advanced drivers, and system-level control algorithms to ensure that the 800V high voltage is rock-solid at the first stage when inputting into data centers.
Renesas: Renesas enters the 800V ecosystem with GaN and power control. In October 2025, Renesas announced support for NVIDIA's 800V DC AI data center architecture. Its solution focuses on GaN power devices, MOSFETs, controllers, and drivers. Renesas states that GaN devices facilitate fast switching, reduce energy loss, and improve thermal management; its GaN solution supports DC/DC conversion from 48V to 400V and can be stacked up to 800V, with converters based on LLC DCX topologies achieving efficiencies of up to 98%.
Another neglected simulated battlefield:
High-speed signal chain
Besides power management, AI has also ignited another sub-segment of analog chips—high-speed signal chains (Retimer/Redriver chips).
The essence of AI servers is not simply cramming more GPUs into a rack, but rather creating a high-throughput, low-latency, and scalable data system between GPUs, CPUs, DPUs, network cards, SSDs, CXL memory, and switching chips. With PCIe 6.0 increasing to 64GT/s and PCIe 7.0 further targeting 128GT/s, signals become severely distorted after traveling only a few centimeters on the PCB. This necessitates a dense array of high-performance analog mixed-signal chips on the server motherboard to repair, compensate, and regenerate signals, such as Retimers, Redrivers, Clock Buffers, Jitter Attenuators, CDRs, PLLs, and high-speed SerDes analog front-ends.
These products are precisely the areas of expertise that traditional analog chip manufacturers have accumulated over a long period of time.
Taking TI as an example, it already has a relatively complete product and technology reserve in the field of PCIe Redriver/Retimer. According to TI's official data, its PCIe 5.0 linear Redriver is designed for high-speed interfaces such as 32Gbps PCIe 5.0, CXL, and UPI 2.0, and can provide up to 24dB CTLE boost, 100ps ultra-low latency, and support x4, x8, and x16 PCIe bus widths.
Renesas primarily focuses on clock and timing chips. High-speed links in AI servers not only require clean data channels but also sufficiently low clock jitter. Renesas launched a complete PCIe clocking solution for data centers and network infrastructure as early as the PCIe Gen5 stage; and in the PCIe Gen6 stage, it launched a portfolio of clock buffers and multiplexers compliant with PCIe Gen6 specifications. These new devices are specifically designed for low-jitter clock distribution in servers, high-performance computing, and data center platforms.
ADI's data center solutions cover power management, optical interconnect control, and sensing solutions in high-density servers, storage, and network systems; its high-performance clock and jitter attenuator products have long served high-speed data converters, JESD204B, and other high-speed interface scenarios. For example, ADI's HMC7044 is a dual-loop integer N jitter attenuator used to provide ultra-low phase noise clocks for high-speed data converters.
In 2025, Microchip announced the expansion of its connectivity, storage, and compute product portfolio for AI data centers, emphasizing its commitment to meeting the bandwidth, performance, security, and management needs of AI data centers. Its XpressConnect Retimer product supports PCIe Gen5 and CXL 2.0, targeting high-performance PCIe applications, CXL memory, and GPU connectivity scenarios. Microchip emphasizes its low latency, diagnostic capabilities, multiple configuration options, and low power consumption.
For example, Semtech directly calls this line Signal Integrity. According to Semtech's official information, its data center signal integrity product portfolio targets optical and copper interconnects, serving AI workloads, cloud computing, and enterprise networks; its Tri-Edge platform is a CDR technology for PAM4 optical interconnects, used in 200G, 400G, and other data center modules and AOC applications.
High-speed signal chains are not a peripheral part of the AI industry chain, but rather another main avenue for analog chip manufacturers to enter AI infrastructure . Their logic is highly similar to power management: power management addresses the issue of "efficient power delivery" for AI chips, while high-speed signal chains address the issue of "stable data flow" in AI systems.
In general, the more powerful the GPU, the higher the power consumption, the larger the data throughput, and the more complex the interconnect links within the server, the stronger the presence of analog chip manufacturers at both the power and signal ends.
Conclusion
While the AI boom is now reaching analog chips, it's crucial to recognize that this isn't a universally beneficial industry boom. The global analog chip industry remains in a complex cyclical adjustment phase. Consumer electronics analog chips, general-purpose PMICs, traditional industrial analog chips, and even some conventional automotive-grade chips continue to face overcapacity and price wars.
In this AI feast, the ones who truly reap the greatest rewards are the leading players who possess high-performance high-voltage isolation, high-power GaN/SiC integration capabilities, high-speed low-latency signal chains, and the ability to master high-barrier technologies such as "package-level/vertical power supply".
ADI's $1.5 billion gamble on Empower is just the beginning. With the full rollout of NVIDIA's 800V data center ecosystem in 2027, the Matthew effect in the analog semiconductor industry will be further amplified. In this battle for power and signal strength in the second half of the AI era, whoever gets closer to the core of computing power will hold the power to define the industry for the next decade.
For domestic manufacturers, how to break through in this market dominated by giants will be a key focus. Let's wait and see!
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This article is from the WeChat Official Account "Semiconductor Industry Observer" (ID: icbank), author: Du Qin DQ
