According to a report by Bloomberg, TSMC's US division president Rick Cassidy said in a webinar on Wednesday that the yield rate of chip production at TSMC's Phoenix factory is about 4% higher than that of similar factories in Taiwan. Yield rate is a key performance indicator in the semiconductor industry, determining a company's ability to bear the huge costs of chip factories.
Breakthrough in TSMC's US factory yield
This symbolizes progress in the US efforts to revive semiconductor manufacturing. As a major chip manufacturing partner for companies like NVIDIA and Apple, TSMC is expected to receive $6.6 billion in government subsidies and $5 billion in loans, plus a 25% tax credit, to build 3 wafer fabs in Arizona, but like almost all other subsidies in the 2022 'Chip Act', the subsidies have not yet been finalized.
A TSMC spokesperson declined to comment on Rick Cassidy's remarks, but mentioned comments made by TSMC CEO CC Wei in an online investor conference last week, where Wei said that the first fab has already started producing engineering wafers using the 4nm process in April, with satisfactory results and very good yields, which is an important operational milestone for TSMC and its customers, demonstrating TSMC's strong manufacturing capabilities and execution.
Intel and Samsung Electronics are the other two major chip manufacturers in the Biden administration's technology strategy, and they have been struggling in recent months, with Intel facing heavy financial pressure, delaying global plans and considering asset sales, while TSMC is progressing smoothly, with better-than-expected quarterly results and an upward revision of its 2024 revenue growth target, and its stock price hitting a new high earlier this month.
Bloomberg points out that TSMC's latest yield improvement is noteworthy, as TSMC has traditionally kept its most advanced and highest-performance factories in Taiwan, while the Arizona factory initially faced challenges due to a lack of skilled workers to install advanced equipment, and the workforce also faced safety and management issues, until an agreement was reached with the union at the end of last year.
TSMC originally planned for the first Arizona fab to be in full production by 2024, but due to labor issues, this has been delayed to 2025, and the second fab, originally scheduled for 2026, has also been pushed back to 2027 or 2028. Rick Cassidy mentioned that TSMC may want to further expand its business in the US, which depends on whether it can receive more government support, and the Phoenix campus can accommodate at least 6 wafer fabs.
TSMC's 5nm and below pricing reported to rise further
Meanwhile, according to a report by DIGITIMES, chip makers have revealed that TSMC has recently released 2025 foundry pricing to multiple customers, with 5/4/3nm process pricing rising again, exceeding the previously estimated 4% range, reaching as high as 10%, varying by customer, product and capacity scale and tier.
It is understood that as advanced processes and advanced packaging technologies continue to progress, the deployment cost of 2nm is beginning to bring gross margin erosion, coupled with inflationary pressures and high overseas fab construction costs, causing TSMC's foundry pricing to rise significantly, with orders for AI-related HPC products seeing an increase of about 8-10%, and mobile communications customers seeing around 6%.
As TSMC has a near-monopoly in 5nm and below, the risk of process lagging and low yields is huge for customers turning to Samsung Electronics or Intel, and TSMC's 5/4/3nm capacity is fully loaded, with other fabs struggling to compete for capacity, coupled with strong AI and HPC demand and the fear of missing the AI train, customers can only accept the price hikes with tears.
Chip makers reveal that TSMC has been confirming its 2nm product roadmap to customers, with foundry pricing surging above $30,000, and customers, unable to shift orders to Samsung or Intel, can only start releasing orders according to TSMC's timeline, which is the key to TSMC's ability to fully control the 2nm capacity scale.
